Technological advances such as those presently occurring in logic design, are dependent upon the availability of hermetic semiconductor packages having a high input/output terminal density, and being capable of high power dissipation. Logic chips or die packaged in hermetic single chip packages have historically been the basic element in the design of most electrical equipment. All of the single chip packages that are commercially available utilize a logic die that has its input/output connections made to signal pads disposed along the die periphery. These peripheral pads are connected by wire bonding or Tape Automated Bonding (TAB) to a substrate which fans out to peripheral leads on a larger pitch or to an array of area pins on the substrate. For a high power area pin package, the package size is often increased to provide for thermal conduction through the back of the die. Effectively, all single chip packages available today utilize leads on the edge of the die and fan out to a larger pitch for the next level of interconnect resulting in decreased chip density and increased load capacity.
In the development of high performance digital computers, a multichip approach has been utilized wherein a number of non-hermetic, bare die have been connected in an assembly that is enclosed by a unitary hermetic cover. This multichip assembly provides higher performance than single chip packaging by reducing interconnect lengths and chip input capacity. However, the multichip approach requires a sophisticated assembly process and has a significant disadvantage in that repair to any of the multiplicity of die connections is difficult to effect.
What is desired is a hermetic single chip package that allows the spacing among a plurality of chips to be substantially equivalent to that provided by the multichip organization and at the same time has a low input capacity. The present micro integrated circuit package fills such a need.